An electrostatic discharge (ESD) event occurs when there is a transfer of energy between bodies that have different electrostatic potentials, either through contact or through an ionized ambient discharge. Integrated circuits (ICs) with inadequate ESD protection are subject to catastrophic failure, including, e.g., ruptured passivation, electrothermal migration, splattered aluminum, contact spiking, dielectric failure and the like. Alternatively, an ESD event can damage a device even though the device continues to function. Damage of this type constitutes latent defects, which are hard to detect and significantly shorten the life of such damaged ICs.
Under the conventional art, it is common to rely on the physical and electrical size of output (e.g., off-chip) driver circuits, to provide electrostatic discharge protection. The output driver itself generally provides for enhanced ESD protection through the use of a large total width of a multiple-finger structure and a wide contact-to-poly spacing.
However, the effectiveness of this conventional approach to electrostatic discharge protection has been decreasing as integrated circuit technology advances. The general trend of ever smaller device geometry and decreasing circuit area favors a decreasing chip size. Accordingly, the die area available for output circuits continues to decrease, which lessens the ESD absorption/mitigation capabilities of such output circuits.
Unfortunately, there is a growing need for even higher levels of electrostatic discharge protection than before. This promotes use of an independent ESD device in parallel with the output driver for ESD protection.
In general, the gate of an output driver is connected to an internal circuit, e.g., to receive the signal to be output. This form of connection generally makes the output device snapback much faster in response to an ESD event than if the gate of the output driver was grounded. In order to fully protect the output driver, a separate ESD device must have a trigger voltage lower than a breakdown voltage of the output driver, as well as having an ultra-low on-resistance even in a high ESD current regime.
As used herein, the term breakdown voltage refers to both oxide breakdown voltage as well as junction breakdown voltage. In general, the lower of these two voltages is a point at which an integrated circuit fails to operate, and actual physical damage may occur. Either of these voltages may be lower than the other (in magnitude) depending upon a wide variety of construction and process variables.
An ESD protection device should also have a holding voltage greater than the maximum operating voltage of the circuit to prevent the circuit from turning on during an ESD event. Otherwise the circuit may be permanently damaged due to high ESD currents that cannot be sustained by the circuit itself. When the snapback trigger voltage is greater than a breakdown voltage, damage to the integrated circuit can occur if an ESD event causes a voltage that is greater than the lowest breakdown voltage.
IC manufacturers attempt to design metal oxide semiconductor field effect transistors (MOSFETs) that have a desirable relationship between snapback trigger voltage and snapback holding voltage for use in ESD protection devices for IC applications. However, these parameters are constrained by the IC manufacturing process and by circuit performance considerations. Thus, an optimal combination of snapback trigger voltage and snapback holding voltage is not always available.